The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a lightly doped drain (LDD) region of a field effect transistor, and more particularly to the manufacture of a complementary metal oxide semiconductor (CMOS) field effect transistor, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as metal oxide semiconductor (MOS) field effect transistors, bipolar complementary metal oxide semiconductor (BiCMOS) field effect transistors, among others.
Industry utilizes or has proposed several techniques for the manufacture of a CMOS integrated circuit device, and in particular an LDD CMOS fabrication method. An example of a fabrication process includes steps of defining a gate electrode onto a well region. By way of the gate electrode, an LDD region is formed onto the well region by a self-aligned implant process. Sidewall spacers are then formed on gate electrode sides by a chemical vapor deposition (CVD) technique. A second higher dose implant is then performed within the periphery of the LDD region. The combination of the LDD region and the second higher dose implant defines source/drain regions for the CMOS device. Details of such LDD for CMOS fabrication are illustrated by FIGS. 1-13 below.
A limitation with an LDD structure for a conventional CMOS device is sidewall spacer dimensions are often difficult to control as device geometry decreases. For example, the gate electrode of the conventional device is about 1 micron and below. Accordingly, the sidewall spacers include a corresponding width of about 0.2 micron and less. A conventional fabrication technique for forming such sidewall spacer is by way of CVD formation of an oxide layer, and a subsequent step of anisotropic etching, typically either reactive ion etching or plasma etching. The step of anisotropic etching is often extremely difficult to control accurately, at the smaller dimensions, thereby causing a large variation in spacer width. The large variation in spacer widths creates devices with differing switching characteristics, which is clearly an undesirable result.
Another limitation with the LDD structure of the conventional CMOS device includes hot electron injection effects, typically electrons inject into the sidewall spacers. The conventional LDD structure often locates more of the N- type (for an NMOS) or P- type (for a PMOS) region outside a region directly underlying a gate electrode, that is, a greater portion of the N- type region or P- type region is underneath the sidewall spacers, rather than directly beneath the gate electrode. When voltage at the gate electrode turns the device on, hot electrons inject into the sidewall spacers, often increasing the resistance in the LDD region directly underneath the sidewall spacers. This tends to cause the LDD regions underneath the sidewall spacers to "pinch off" by way of the higher resistance. Other limitations include a threshold voltage variation, a saturated current variation, a transconductance degradation, and the like.
A PMOS device used in conventional CMOS technology, and in particular an LDD region for the PMOS device includes a further limitation of difficulty with a P- type threshold implant step. The conventional PMOS device has oxide spacers made by CVD which are thick, relative to other device dimensions. In fact, the oxide spacers thicknesses range from about 1,500 .ANG. to about 2,000 .ANG.. This means the P- type implant is often deep, and therefore difficult to control. The difficulty in controlling the implant often creates an inconsistent resulting implant. By the inconsistent implant, the conventional PMOS device is often difficult to reduce in size. A punch-through effect is also difficult to control in the conventional PMOS device, as device dimension decreases.
Still further, it is often desirable to reduce defects in a wafer introduced during its processing. Wafer fabrication processes such as masking, exposing, developing, etching, and others typically introduce particles into an integrated circuit. These particles contribute to the amount of defective integrated circuit chips. Generally, more masks used in a semiconductor process tends to contribute to more defective integrated circuit chips. For example, a conventional CMOS process relies on at least five separate masks to form the LDD and source/drain regions for NMOS and PMOS devices. As industry attempts to increase the yield of good integrated circuit chips on a wafer, it is often desirable to reduce the number of masks (or masking steps) used during wafer manufacture.
From the above it is seen that a method of fabricating a semiconductor LDD structure that is easy, reliable, faster, and cost effective, is often desired.